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IDProjectCategoryView StatusDate SubmittedLast Update
0000628T99X171.00 SKB EagleHW Issuepublic2019-04-18 14:222019-04-24 22:03
Reporter(ALTech) SB ParkAssigned To(HW) Sean Chiang Due Date2019-04-23 15:03
PriorityimmediateSeveritys2-severeReproducibilityalways
Status closedResolutionfixed 
Summary0000628: [Eagle] the rebooting infinite loop during power on
Descriptionthe Eagle board has a defect. Mr Kerwin will hand carry this board. debug please and find root cause.
1. symtom
    1) LED : RED LED is turn on and stay (do not change white color)
    2) HDMI : No HDMI output
2. check point
    1) Log message (see attached file)
        - Cfg max: 5, cur: 5. Board id: 255. Force loop cfg
           LPDDR3 probe
           Firmware does not exist!
           All ddr config failed...
           Reset...
           boot times 4G12A:BL:0253b8:61aa2d;FEAT:E0F93180:2000;POC:F;RCY:0;EMMC:0;READ:0;0.0?
                                                                                   bl2_stage_init 0x01
            ------------- then rebooting -----------------------
     2) power
         1) there is no power output of U304 (I cannot check all power rail because Foxconn does not share the schematic)
         2) clock (y401) may normal operate (my scope is very poor. I just can catch the dc level of xtal)
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Users monitoring this issue

User List (HW) Jim Liang , (HW) Sean Chiang , (RD) Fu-chiang Young

Activities

(ALTech) SB Park

2019-04-18 14:22

developer  

AE5_U304gif.gif (206,432 bytes)   
AE5_U304gif.gif (206,432 bytes)   
bootingfail_log_AE5.txt (8,153 bytes)    
                                                                                  bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:00000701
L2:00008067
L3:04000000
S1:00000000
B2:00002000
B1:e0f93180

TE: 130831

BL2 Built : 10:46:59, Jan 14 2019. g12a g152d217 - guotai.shen@droid11-sz

Board ID = 1
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
sd/emmc cmd 8 arg 0x00000000 status 01ff3000
DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:46:56
board id: 1
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 5, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : STREAM 0x00690001 - 0x00000000
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 5, cur: 2. Board id: 255. Force loop cfg
DDR3 probe
ddr clk to 912MHz
Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : STREAM 0x00490002 - 0x00000000 0x00000000
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 5, cur: 3. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1392MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : STREAM 0x00b00001 - 0x00001000
INFO : STREAM 0x00a70001 - 0x0000001c
INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a
INFO : STREAM 0x00560006 - 0x00000003 0x00000003 0x00001001 0x0000000a 0x00000000 0x00000ae0
INFO : STREAM 0x005b0005 - 0x00000000 0x00000054 0x000000ad 0x00000033 0x00000000
INFO : STREAM 0x00a10000 -
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
Check phy result
INFO : STREAM 0x00b00001 - 0x00001000
INFO : STREAM 0x00a70001 - 0x0000001c
INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a
INFO : STREAM 0x00560006 - 0x00000003 0x00000003 0x0000031f 0x0000000a 0x00000000 0x00000ae0
INFO : STREAM 0x005b0005 - 0x00000000 0x00000054 0x000000ad 0x00000033 0x00000000
INFO : End of initialization
INFO : STREAM 0x00670000 -
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 5, cur: 4. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1392MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : STREAM 0x00b00001 - 0x00001000
INFO : STREAM 0x00a70001 - 0x0000001c
INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a
INFO : STREAM 0x00560006 - 0x00000001 0x00000001 0x00001001 0x0000000a 0x00000000 0x00000ae0
INFO : STREAM 0x005b0005 - 0x00000000 0x00000054 0x000000ad 0x00000033 0x00000000
INFO : STREAM 0x00a10000 -
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
Check phy result
INFO : STREAM 0x00b00001 - 0x00001000
INFO : STREAM 0x00a70001 - 0x0000001c
INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a
INFO : STREAM 0x00560006 - 0x00000001 0x00000001 0x0000031f 0x0000000a 0x00000000 0x00000ae0
INFO : STREAM 0x005b0005 - 0x00000000 0x00000054 0x000000ad 0x00000033 0x00000000
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : STREAM 0x00490002 - 0x00000000 0x00000000
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 5, cur: 5. Board id: 255. Force loop cfg
LPDDR3 probe
Firmware does not exist!
All ddr config failed...
Reset...
boot times 4G12A:BL:0253b8:61aa2d;FEAT:E0F93180:2000;POC:F;RCY:0;EMMC:0;READ:0;0.0?
                                                                                   bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:00000701
L2:00008067
L3:04000000
S1:00000000
B2:00002000
B1:e0f93180

TE: 130501

BL2 Built : 10:46:59, Jan 14 2019. g12a g152d217 - guotai.shen@droid11-sz

Board ID = 1
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
sd/emmc cmd 8 arg 0x00000000 status a1ff3000
DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Jan 14 2019 10:46:56
board id: 1
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
Cfg max: 5, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : STREAM 0x00690001 - 0x00000000
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 5, cur: 2. Board id: 255. Force loop cfg
DDR3 probe
ddr clk to 912MHz
Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : STREAM 0x00490002 - 0x00000000 0x00000000
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 5, cur: 3. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1392MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : STREAM 0x00b00001 - 0x00001000
INFO : STREAM 0x00a70001 - 0x0000001c
INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a
INFO : STREAM 0x00560006 - 0x00000003 0x00000003 0x00001001 0x0000000a 0x00000000 0x00000ae0
INFO : STREAM 0x005b0005 - 0x00000000 0x00000054 0x000000ad 0x00000033 0x00000000
INFO : STREAM 0x00a10000 -
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
Check phy result
INFO : STREAM 0x00b00001 - 0x00001000
INFO : STREAM 0x00a70001 - 0x0000001c
INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a
INFO : STREAM 0x00560006 - 0x00000003 0x00000003 0x0000031f 0x0000000a 0x00000000 0x00000ae0
INFO : STREAM 0x005b0005 - 0x00000000 0x00000054 0x000000ad 0x00000033 0x00000000
INFO : End of initialization
INFO : STREAM 0x00670000 -
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 5, cur: 4. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1392MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : STREAM 0x00b00001 - 0x00001000
INFO : STREAM 0x00a70001 - 0x0000001c
INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a
INFO : STREAM 0x00560006 - 0x00000001 0x00000001 0x00001001 0x0000000a 0x00000000 0x00000ae0
INFO : STREAM 0x005b0005 - 0x00000000 0x00000054 0x000000ad 0x00000033 0x00000000
INFO : STREAM 0x00a10000 -
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
Check phy result
INFO : STREAM 0x00b00001 - 0x00001000
INFO : STREAM 0x00a70001 - 0x0000001c
INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a
INFO : STREAM 0x00560006 - 0x00000001 0x00000001 0x0000031f 0x0000000a 0x00000000 0x00000ae0
INFO : STREAM 0x005b0005 - 0x00000000 0x00000054 0x000000ad 0x00000033 0x00000000
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : STREAM 0x00490002 - 0x00000000 0x00000000
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 5, cur: 5. Board id: 255. Force loop cfg
LPDDR3 probe
Firmware does not exist!
All ddr config failed...
Reset...
bootingfail_log_AE5.txt (8,153 bytes)   

(HW) Sean Chiang

2019-04-22 09:23

developer   ~0002104

Hi SB,
Have received this failed board from Kerwin this morning. Will check it and give you an update when we find the root cause.


Hi Fu-Chiang,
Please analyze the failed symptom and debug the board.

(RD) Fu-chiang Young

2019-04-22 15:33

developer   ~0002113

Hi SB,
We check the unit and power rail, found the U304 was no output at P1V2. This power is for DDR.
Check the console and found DDR fail log was shown up.
So change a new U304 power IC and unit can boot up.
Thank you.
137325.jpg (280,878 bytes)

(ALTech) SB Park

2019-04-22 15:49

developer   ~0002115

Hi Sean, Fu-Chiang
Thank you very much for repairing board. I think the most important thing is finding the root cause rather than repairing it. please find why U304 was dead.

(ALTech) SB Park

2019-04-22 15:51

developer   ~0002116

Hi Sean.
If someone has a business trip to Korea in near future, please ask that person to handcarry the board.

(HW) Sean Chiang

2019-04-22 16:17

developer   ~0002117

Hi SB,
Our SW Engineer Jim will have biz trip to your office at Korea this Wed.(4/23). We will try to fix this board tomorrow and let Jim to return the board to you on this Wed.

(ALTech) SB Park

2019-04-22 16:22

developer   ~0002118

Hi Sean
thank you

(RD) Fu-chiang Young

2019-04-22 19:19

developer   ~0002126

Hi SB,
Here is the FA report.
Thank you.
0000628_Failure Analysis Report_V1.pdf (446,030 bytes)

(ALTech) SB Park

2019-04-22 22:14

developer   ~0002130

Hi Fu-chiang Young. thank you for the report.
but, this board was covered by acryl mockup. so there is no finger touch. there is little chance of damage by ESD.

(ALTech) SB Park

2019-04-24 20:42

developer   ~0002185

HI Sean
Please update your comment of this issue. and I will close this issue.

(HW) Sean Chiang

2019-04-24 21:45

developer   ~0002186

Hi SB,
As per my comment in the weekly meeting, since this board was shipped out in EVT build and there is no housing assembled with PCBA in that time. So, there were have high risk from ESD damage when engineer using the board. Also, in EVT stage, the QA team of vendor will not accept the defect IC from RD site since our boards is not built by normal production line from MFG site. So, what we can do now is to debug the defect board and fix it. But it's not possible to do further analyze for failed IC.

Issue History

Date Modified Username Field Change
2019-04-18 14:22 (ALTech) SB Park New Issue
2019-04-18 14:22 (ALTech) SB Park Status new => assigned
2019-04-18 14:22 (ALTech) SB Park Assigned To => (HW) Sean Chiang
2019-04-18 14:22 (ALTech) SB Park File Added: AE5_U304gif.gif
2019-04-18 14:22 (ALTech) SB Park File Added: bootingfail_log_AE5.txt
2019-04-18 14:22 (ALTech) SB Park Description Updated
2019-04-22 09:15 (HW) Sean Chiang Issue Monitored: (RD) Fu-chiang Young
2019-04-22 09:15 (HW) Sean Chiang Issue Monitored: (HW) Jim Liang
2019-04-22 09:16 (HW) Sean Chiang Issue Monitored: (HW) Sean Chiang
2019-04-22 09:23 (HW) Sean Chiang Note Added: 0002104
2019-04-22 15:33 (RD) Fu-chiang Young File Added: 137325.jpg
2019-04-22 15:33 (RD) Fu-chiang Young Note Added: 0002113
2019-04-22 15:49 (ALTech) SB Park Note Added: 0002115
2019-04-22 15:51 (ALTech) SB Park Note Added: 0002116
2019-04-22 16:17 (HW) Sean Chiang Note Added: 0002117
2019-04-22 16:22 (ALTech) SB Park Note Added: 0002118
2019-04-22 19:19 (RD) Fu-chiang Young File Added: 0000628_Failure Analysis Report_V1.pdf
2019-04-22 19:19 (RD) Fu-chiang Young Note Added: 0002126
2019-04-22 22:14 (ALTech) SB Park Note Added: 0002130
2019-04-24 20:42 (ALTech) SB Park Note Added: 0002185
2019-04-24 21:45 (HW) Sean Chiang Note Added: 0002186
2019-04-24 22:03 (ALTech) SB Park Status assigned => closed
2019-04-24 22:03 (ALTech) SB Park Resolution open => fixed